1. Field of the Invention
The present invention generally relates to an input/output interface between a plurality of integrated-circuit chips, and particularly relates to an input/output interface coping with both high-speed data transfer using high-frequency signals and low-speed data transfer using low-frequency signals.
2. Description of the Related Art
An increase in processing speed of microprocessors should be accompanied by an increase in data-transfer speed using signals of higher frequencies for data transfer between LSI chips. The TTL level and the CMOS level used as input/output levels in the related-art LSIs suffer from increasing effects of signal reflections and crosstalk when a signal frequency becomes as high as about 50 MHz. These effects make it difficult to conduct error-free data transfer.
In order to obviate this problem, various input/output interfaces such as CTT (center tapped termination) and GTL (Gunning transceiver logic) use signals of small amplitudes lower than 1V. These input/output interface schemes are not satisfactory enough, however, when frequency limits and chip-power consumption are considered.
In light of these, the inventor of the present invention has proposed high-speed and small-signal-amplitude interface standard SSTL (stub series terminated logic), which was adopted by JEDEC (a lower branch of the Electronics Industries Association in the United States) as an industry standard.
FIG. 1 is an illustrative drawing showing a bus configuration of SSTL.
As shown in FIG. 1, SSTL inserts resistance Rs between a bus 10 having a characteristic impedance Z.sub.0 and a stub (branch from the bus 10) 11 having a characteristic impedance Z.sub.1. This resistance Rs has a resistance value related as: EQU Z.sub.0 /2+Rs=Z.sub.1 ( 1)
In this case, a signal reflected at a device end and returning to the bus 10 will not be reflected again at the connection between the stub 11 and the bus 10, because impedance matching is in place between the stub 11 and a point beyond (bus 10). This prevents transient responses from interfering with transmitted signals, thereby achieving high-speed data transfer. SSTL also connects the bus 10 to the termination voltage Vtt via termination resistances Rt as shown in FIG. 1. The termination voltage Vtt is set lower than a power voltage level. Choice of an appropriate value for the termination resistance Rt can prevent signal reflections at the end points of the bus 10.
In practice, the termination voltage Vtt is substantially 1.5V, and a reference voltage Vref used in receivers (input units for receiving signals from the bus) is also substantially set to 1.5V. The termination resistance Rt is about 50 .OMEGA., and the resistance Rs is approximately 25 .OMEGA..
The SSTL described above can achieve high-speed data transfer, but has a problem in terms of power consumption. Personal computers and engineering workstations are generally provided with a function to reduce a clock frequency for power conservation. This function may be activated when no input entry from a keyboard is made for a predetermined time period. However, systems complying with the SSTL standard require input buffers for high-speed data transfer to be provided on the input side of devices, and these input buffers consume a large amount of power. On the side of the bus, also, the terminal resistances Rt consume power. These factors prevent the SSTL systems from achieving a sufficient reduction in power consumption even when the clock frequency is reduced.
Accordingly, an SSTL system needs an input/output interface and a bus configuration which achieve a sufficient reduction in power consumption by switching from a high-speed transfer mode to a low-speed transfer mode.
Considering the main objective of SSTL which is to achieve high-speed data transfer, it is desirable if high-speed characteristics of SSTL are further enhanced. This may be achieved by incorporating into chips used in SSTL systems some features which can enhance the high-speed characteristics of the system. It is preferable, however, to be able to use the same chips in LVTTL systems as well as in SSTL systems, in consideration of the diversity of chip usage.
In general, chips for SSTL are usable in LVTTL without any change. Namely, these chips can be built in a low-speed system using LVTTL, and, at the same time, can be built in a high-speed system using SSTL. If such features as enhancing the high-speed characteristics of SSTL are incorporated into these chips by specializing the chips, these chips may not be usable in LVTTL systems.
Accordingly, it is desirable to have an input/output interface which enhances the high-speed characteristics of SSTL and is usable in LVTTL systems, and a chip having such an input/output interface.
Accordingly, there is a need in SSTL for an input/output interface and a bus configuration which can achieve a sufficient reduction in power consumption by switching from a high-speed transfer mode to a low-speed transfer mode.
Also, there are needs for an input/output interface which can enhance the high-speed characteristics of SSTL and yet be usable in LVTTL systems, and for a chip having such an input/output interface.